عنوان پایان‌نامه
افزایش قابلیت اطمینان در معماری های چند هسته ای با استفاده ازپیکربندی مجدد
- رشته تحصیلی
- مهندسی کامپیوتر-معماری کامپیوتر
- مقطع تحصیلی
- کارشناسی ارشد
- محل دفاع
- کتابخانه دانشکده برق و کامپیوتر شماره ثبت: E2043;کتابخانه مرکزی -تالار اطلاع رسانی شماره ثبت: 53138;کتابخانه مرکزی پردیس 2 فنی شماره ثبت: E 2043
- تاریخ دفاع
- ۳۰ خرداد ۱۳۹۱
- دانشجو
- رضا نخجوانی
- استاد راهنما
- سعید صفری
- چکیده
- نیاز روز افزون به سیستم هایی با توان محاسباتی و کارایی بالا از یک سو وافزایش پیچیدگی مدارهای دیجیتال از سوی دیگر مسیر طراحی را به سوی سامانه های مبتنی بر سیستم روی تراشه سوق داده است این افزایش پیچیدگی در کنار کاهش ابعاد ترانزیستورها جداسازی فعالیت قسمت های محاسباتی و ارتباطی در تراشه های امروزی را به امری اجتناب ناپذیر بدل نموده است.
- Abstract
- The ever increasing demand for high performance systems, along with the deep submicron feature size in the state of the art fabrication process, and the imposed complexity of the modern VLSI circuits, have led us to integrate pre-designed and pre-verified Intellectual Property (IP) cores into a single chip, called System-on-Chip (SoC). Network-on-Chip (NoC) design paradigm seems to be a promising solution for the productivity gap in such systems. However, due to the limited floor-planning options, physical mapping of a large number of cores with several memory blocks into a single chip using 2D-NoC architecture is very difficult if not impossible. Integration of Three-dimensional (3D) ICs technology with NoC design methodology, not only opens a wide range of possibilities to obtain more performance improvements, but also leads to lower power consumption and higher noise immunity. Although considerable improvements in fabrication process and technology scaling enable us to shorten NoC interconnection network, it makes the products more and more susceptible to the permanent manufacturing faults due to the stochastic variations of the physical design parameters. In this research, a method is proposed to gracefully degrade 3D on-chip networks in the presence of some faulty links. Thus, when there is no faulty links in the circuit, all of the links would cooperate to route the packets, and when some faulty links are detected, after a reconfiguration step, the system stays functional using the remaining non-faulty links. Of course, the degraded circuit will have lower performance due to the decreased number of available communication links. First, an efficient and scalable router for network switches is introduced which utilizes a fixed size programmable routing table (PRT). Then, we propose a heuristic search algorithm to find a valid configuration for PRTs to compensate the effect of faulty links in three dimensional on-chip networks. The proposed algorithm considerably reduces the required search effort as compared to the exhaustive search method. An investigation of the proposed algorithm behavior among different fault patterns has been performed. This analysis provides the ability of determining fault patterns which are solvable/non-solvable by our algorithm. Therefore it would be possible to determine whether it worth searching for a valid configuration or not.
