عنوان پایان‌نامه
طراحی برای آزمون پذیری در سطح سیستم
- رشته تحصیلی
- مهندسی کامپیوتر-معماری کامپیوتر
- مقطع تحصیلی
- کارشناسی ارشد
- محل دفاع
- کتابخانه دانشکده برق و کامپیوتر شماره ثبت: E1975;کتابخانه مرکزی -تالار اطلاع رسانی شماره ثبت: 50548
- تاریخ دفاع
- ۳۱ شهریور ۱۳۹۰
- دانشجو
- فاطمه جواهری
- استاد راهنما
- زین العابدین نوابی شیرازی
- چکیده
- با افزایش پیچیدگی سیستم های دیجیتال طراحی در سطح سیستم به عنوان روش طراحی این سیستم ها مطرح شده است روش مدل سازی در سطح تراکنش به عنوان اولین قدم در مسیر طراحی دیجیتال در سطح سیستم ارائه شده است. مزیت اصلی این روش امکان جدا سازی بخش های محاسباتی و ارتباطی و صرف نظر از جزئیات مدل سازی و زمان بندی های دقیق سطوح انتزاعی پایین تر می باشد. هر چند که مدل سازی مدارهای دیجیتال در سطح سیستم میسر گشته است. اما آزمون و طراحی برای آزمون پذیری هم چنان در سطوح پایین تر باقی مانده و تحقیقات چندانی بر روی آن در سطح تراکنش صورت نگرفته است.
- Abstract
- The increasing complexity of digital system design has led to introduction of Electronic System Level (ESL) as a higher abstraction level for designing complex systems. Transaction Level Modeling (TLM) has been proposed as the key step toward the ESL methodology. TLM is a transaction-based approach that focuses on separating communication links from processing elements. The focus of TLM is on abstracting the communications, and this is accomplished through passing high-level data structures called transactions between computational parts. Although notable achievements have been gained in designing and modeling systems at ESL, no unified model or common method has been introduced for test at this level. To bridge this gap, new test methods should be considered. At the first step, a hardware-aware ESL design methodology consisting of various architectures and design levels is proposed. A set of abstract communication scenarios is introduced based on the proposed methodology and the OSCI TLM-2.0 standard. A method is proposed for formal representation of these communication scenarios using Timed Automata (TA). This model formalizes, and thus, facilitates the process of verification, synchronization, synthesis, and test. Since the high-level designed systems are going to be on real chips, high-level communication scenarios are mapped to corresponding standard on-chip communications. To do this, the on-chip communications and abstract TLM communication scenarios are modeled formally using Timed Automata. To perform testing, the proposed communication scenarios are represented by TA and considered as the golden models. TA models of communication links are used for generating the faulty communication scenarios automatically. A set of high-level fault models is defined that includes fault model definition for data and control parts of a communication link. TA of faulty System under Design and Test (SUDTs) is generated using the golden TA model by considering the high level fault model and attributes. For each SUDT, a set of signatures is defined based on its behavior. The UPPAAL verifier is then used for evaluating the function of faulty SUDTs by verifying the signatures. The proposed test strategy not only applies to communication links, but also can be used for testing processing elements considering an appropriate fault model. In addition, in order to evaluate the proposed testing strategy, we show how the proposed high-level faults can correspond to gate-level stuck-at faults. It should be mentioned that we do not expect the proposed high-level fault models to cover all the actual faults of the communication hardware. We expect that the defined high-level fault model covers a subset of stuck-at gate-level faults, and not all of them.
